Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.
R ON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the R ON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (“hole redistribution” in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both R ON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band.
We investigate the drift of threshold voltage (V TH ) and on-resistance (R ON ) in p-GaN power HEMTs after being submitted to negative/positive gate stress. Negative (Positive) Gate Stress (NGS/PGS) was applied at a gate-to-source bias of |V NGS | = V PGS = 6 V up to a cumulative stress time of 8×10 3 s at room temperature. We found that during NGS both V TH and R ON increased over stress time, whereas during PGS both parameters decreased and stabilized to the values prior to stress application. This symmetric behavior was maintained after 5 full NGS/PGS stress cycles, indicating the absence of permanent degradation. To further characterize the V TH and R ON transients, the NGS/PGS stress cycles were repeated at different temperatures (T=30-105 °C). While V TH exhibited a strong Τ-dependence (E A ≈ 0.6 eV) during NGS, a negligible variation of the V TH transients with T was found during PGS (E A ≈ 0 eV). Instead, R ON transients exhibited approximately the same T-dependence during both NGS and PGS (E A ≈ 0.3-0.4 eV).
GaN-based devices are getting more common in the power electronics market thanks also to the improvements obtained in their stability and reliability. Further development of the technology in terms of either lateral p-GaN HEMT for low (100-V) to medium (650-V) voltage range or vertical GaN MOSFET for high (>1000-V)) voltage range requires the careful assessment and modeling of the physical mechanisms leading to recoverable and permanent degradation. In this paper, a selection of the key stability/reliability issues are discussed for both lateral GaN HEMTs and vertical GaN MOSCAPs and Trench MOSFETs.
The emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-device-circuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, ${\beta }$ -Ga 2 O 3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware “intrinsic/limiting” safe operating area (SOA) that establishes a priori , i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and suggests strategies to circumvent them.
We discuss the degradation mechanisms of C-doped 0.15-μm gate AlGaN/GaN HEMTs tested by drain step-stress experiments. Experimental results show that these devices exhibit cumulative degradation effects during the step stress experiments in terms of either (i) transconductance (gm) decrease without any threshold-voltage (VT) change under OFF-state stress, or (ii) both VT and gm decrease under ON-state stress conditions. To aid the interpretation of the experiments, two-dimensional hydrodynamic device simulations were carried out. Based on obtained results, we attribute the gm decrease accumulating under OFF-state stress to hole emission from CN acceptor traps in the gate-drain access region of the buffer, resulting in an increase in the drain access resistance. On the other hand, under ON-state stress, channel hot electrons are suggested to be injected into the buffer under the gate and in the gate-drain region where they can be captured by CN traps, leading to VT and gm degradation, respectively.
In this brief, we investigate the bidirectional threshold voltage drift ( ΔV T ) following negative-bias temperature instability (NBTI) stress in carbon-doped fully recessed AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Several stress conditions were applied at different: 1) gate biases ( V GS,STR ); 2) stress times ( t STR ); and 3) temperatures ( T). Both negative and positive ΔV T (thermally activated with different activation energies, E A ) were observed depending on the magnitude of V GS,STR . In accordance with the literature, observed ΔV T <; 0 V ( E A ≈ 0.5 eV) under moderate stress is attributed to the emission of electrons from oxide and interface traps. Instead, ΔV T > 0 V ( E A ≈ 0.9 eV) under high stress is attributed to the increased negatively ionized acceptor trap density in the buffer associated with carbon doping.
Various large-area growth methods for two-dimensional transition metal dichalcogenides have been developed recently for future electronic and photonic applications. However, they have not yet been employed for synthesizing active pixel image sensors. Here, we report on an active pixel image sensor array with a bilayer MoS2 film prepared via a two-step large-area growth method. The active pixel of image sensor is composed of 2D MoS2 switching transistors and 2D MoS2 phototransistors. The maximum photoresponsivity (Rph) of the bilayer MoS2 phototransistors in an 8 × 8 active pixel image sensor array is statistically measured as high as 119.16 A W-1. With the aid of computational modeling, we find that the main mechanism for the high Rph of the bilayer MoS2 phototransistor is a photo-gating effect by the holes trapped at subgap states. The image-sensing characteristics of the bilayer MoS2 active pixel image sensor array are successfully investigated using light stencil projection.
In this article, we present coupled experimental/simulated results about the influence of interface and border traps on the electrical characteristics and split‐CV mobility extraction in InGaAs MOSFETs. These results show that border traps limit the maximum drain current under on‐state conditions, induce a hysteresis in the quasi‐static transfer characteristics, as well as affect CV measurements, inducing an increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. Hysteresis in the transfer characteristics can be used as a sensitive monitor of border traps, as suggested by a sensitivity analysis where either the energetic or the spatial distribution of border traps are varied. Finally, we show that mobility extraction by means of the split‐CV method is affected by appreciable errors related to the spurious contributions of interface and border traps to the total gate charge, ultimately resulting in significant channel mobility underestimation. In very narrow channel devices, channel electron spilling over the InP buffer layer can also contribute to mobility measurement inaccuracy.
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