P. Uma Sathyakam

Vellore Institute of Technology University

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P. S. Mallick

Vellore Institute of Technology University

S. Harish

Vellore Institute of Technology University

A. Karthikeyan

Vellore Institute of Technology University

Muzammil Mushtaq

Vellore Institute of Technology University

Annamalai Senthil Kumar

Vellore Institute of Technology University

Shubham Raj

Indian Institute of Technology Kharagpur

Ananyo Banerjee

Vellore Institute of Technology University

Vijayaraghavan Rajagopalan

Vellore Institute of Technology University

M. Shefali

Osmania University

Muhammad Hamza

University of Lahore

Cooperative Institutions

Vellore Institute of Technology University

National Institute Of Technology Silchar

Osmania University

GITAM University

Narsee Monjee Institute of Management Studies

SRM Institute of Science and Technology

Saveetha University

Czech Academy of Sciences, Institute of Biotechnology

University of Tennessee at Knoxville

Texas Tech University

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A PSO based optimal repeater insertion technique for carbon nanotube interconnects

International Journal of Electronics Letters (2021)

P. Uma Sathyakam Shubham Raj A. Karthikeyan P. S. Mallick

Optimal repeater insertion is important in VLSI(very large scale integration) interconnects to reduce propagation delay and power dissipation. We propose a particle swarm optimisation (PSO)-based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 20 nm and 14 nm technology nodes. First, numerical equations for optimal repeaters are modelled. Secondly, a PSO-based algorithm is developed and various input parameters are used to train the PSO. Optimal number of repeaters and the propagation delay for CNT interconnects for lengths ranging from 500 to 2000 µm are found out. Results are compared for both numerical and PSO methods, and it is found that they are within 2% deviation. Although earlier work shows similar findings, we have used CNTFET(carbon nanotube field effect transistor)-based inverters as repeaters in CNT interconnects for the first time. We have carried out the analysis for two values of repeater size, i.e. h = 50 and 75.

Repeater (horology)

Optimal design

10.1080/21681724.2021.1941283

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Mixed CNT bundle interconnects for subthreshold circuits

P. Uma Sathyakam Dipanjan Choudhary P. S. Mallick

Performance of mixed carbon nanotube bundle interconnects are analyzed for subthreshold circuits. As voltage scaling in ULSI ICs lead to performance challenges in delay, power dissipation and the overall performance of interconnects, we simulate two mixed CNT bundle configurations, MCB-1 and MCB-2, to analyze their propagation delay, power dissipated and energy delay product for 500μm interconnect length and at 20nm technology noce. Further, we do crosstalk analysis of the proposed bundles using a driver-interconnect-load model. One line is aggressor and another line is victim. Simulated results shows that MCB that has MWCNTs at the periphery and SWCNTs at the core is ideal for intermediate level interconnect applications.

Subthreshold conduction

Power–delay product

Crosstalk

10.1109/icices.2016.7518845

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Reducing Crosstalk Using Air Gaps

Springer eBooks (2020)

P. Uma Sathyakam P. S. Mallick

Air gap (plumbing)

Crosstalk

10.1007/978-981-15-8888-4_5

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Ultra-low-k Dielectrics in CNT Interconnects

Springer eBooks (2020)

P. Uma Sathyakam P. S. Mallick

Low-k dielectric

High-κ dielectric

Silicon oxide

10.1007/978-981-15-8888-4_4

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Geometry-Based Crosstalk Reduction in CNT Interconnects

Journal of Circuits Systems and Computers (2019)

P. Uma Sathyakam P. S. Mallick Paridhi Singh

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

Crosstalk

Spice

10.1142/s0218126620500942

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Citations (6)

Simulation and fabrication of titanium dioxide thin films for supercapacitor electrode applications

Deleted Journal (2024)

Harish Somala Muhammad Hamza P. Uma Sathyakam Annamalai Senthil Kumar

Titanium Dioxide

10.1142/9789819805365_0010

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Perspective—Prospects and Challenges of Cu-CNT Composite Interconnects

ECS Journal of Solid State Science and Technology (2024)

P. Uma Sathyakam P. S. Mallick Wen‐Sheng Zhao Vinod Kumar Jain Anshuman Barpanda

Abstract This paper examines the present state of the art of Cu-carbon nanotube (Cu-CNT) composite interconnects in terms of modelling and fabrication. Cu-CNT composites show promise as an upcoming material for very large scale integrated interconnects technology. Different studies show different aspects of aligning CNTs in the composite. The differences in these studies are highlighted and a possible way forward to address the ambiguities is presented with the help of finite element simulations of Joule heating and heat propagation in Cu and Cu-CNT interconnects.

10.1149/2162-8777/ada183

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Frequency response analysis of CNT bundle interconnects

International Journal of Electronics Letters (2022)

M. Shefali Kaleem Fatima P. Uma Sathyakam

When carbon nanotubes (CNTs) are used in interconnects, their electrical properties are appealing as they are not affected by surface scattering when the feature size decreases. After almost two decades of research on CNT-based interconnects, it is still a question which type of CNT bundle performs better than the other. There are many contradictory reports in this regard. So, it is very important to study the frequency response of these interconnects to ascertain their actual performance and compare them. HSPICE-based circuit simulations at 20 nm and 14 nm technology nodes are carried out. Furthermore, the analysis for local, semi-global and global interconnect lengths is carried out. Results show that single-walled CNT (SWCNT) bundles have higher voltage gain and higher current gain for all lengths at both the technology nodes. These results are significant in understanding the best choice of interconnects among SWCNT bundle, MWCNT bundle and mixed CNT bundle interconnects.

10.1080/21681724.2022.2117849

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Background

Springer eBooks (2020)

P. Uma Sathyakam P. S. Mallick

Crosstalk

10.1007/978-981-15-8888-4_2

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VHDL Implimentation of a 16-Bit Microprocessor

P. Uma Sathyakam

The objective of this book is to develop the hardware and system software for a 16-bit processor. The design of the processor is based on the instruction set of the processor provided in the book titled “Digital Design and implementation in FPGA” by Dr. Navabi. An assembler using Turbo C as well as an instruction set simulator using MS Excel with VBA is developed and the design is targeted to an FPGA (Field Programmable Gate Array) board for design prototyping that involves testing of various input signals at the output ports. A typical Xilinx Spartan 3E board is used here.

Microprocessor

FPGA prototype

32-bit

Verilog

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