V. Basker

IBM (United States)

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T. Standaert

IBM (United States)

J. Faltermeier

IBM (United States)

H. Bu

University of Chinese Academy of Sciences

B. Doris

IBM (United States)

Mukesh Khare

Indian Institute of Technology Delhi

T. Yamashita

Kyushu University

S. Kanakasabapathy

Lam Research (United States)

Chun-Chen Yeh

National Tsing Hua University

Vamsi Paruchuri

RWTH Aachen University

S. Schmitz

Praxis für Hämatologie und Onkologie

Cooperative Institutions

IBM (United States)

185

GlobalFoundries (United States)

IBM Research - Thomas J. Watson Research Center

Albany Molecular Research (United States)

GlobalFoundries (Germany)

Software Research and Development Consulting

Albany Technical College

IBM Research - Austin

Semiconductor Research Corporation

University at Albany, State University of New York

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Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

2021 IEEE International Electron Devices Meeting (IEDM) (2009)

Hikaru Kawasaki V. Basker T. Yamashita Lin Chen Yu Zhu

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

10.1109/iedm.2009.5424366

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Citations (91)

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

Xin Yang K. Maitra Chun-Chen Yeh P. Zeitzoff M. Raymond

A significant increase in parasitic resistance (R _PARA ) fluctuation is observed when S/D length is getting smaller than the characteristic length (L _TRANS ). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the analytical model. Further R _PARA fluctuation improvement can be realized by optimizing the L _TRANS .

10.1109/soi.2011.6081799

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Citations (7)

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

C-H. Lin B. Greene Tosihide H. YOSIDA J. Cai A. Bryant

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4 ^th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um ² ) memory solution for industry leading 'scale-out' processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for 'scale-up' enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm ² SoCs.

Dram

10.1109/iedm.2014.7046977

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Citations (117)

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Symposium on VLSI Technology (2011)

Takashi Yamashita V. Basker T. Standaert Chun-Chen Yeh T. Yamamoto

FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO=3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.

Ring oscillator

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Citations (34)

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

Bala S. Haran A. Kumar Lahir Shaik Adam Josephine Chang V. Basker

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum ² 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at V _dd =0.9 V. We also present a 0.09 mum ² cell with SNM of 160 mV at V _dd =0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

10.1109/iedm.2008.4796769

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Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

Isaac Lauer N. Loubet S.D. Kim J. A. Ott S. Mignot

We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.

Metal gate

10.1109/vlsit.2015.7223653

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Citations (54)

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Symposium on VLSI Technology (2010)

V. Basker T. Standaert Hikaru Kawasaki Chun-Chen Yeh K. Maitra

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm ² reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE ² ) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Immersion lithography

Fin

Metal gate

10.1109/vlsit.2010.5556135

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Citations (59)

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

A. Paul A. Bryant Terence B. Hook Chun-Chen Yeh V. Kamineni

A first time rigorous experimental study of effective current (I _eff ) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (A _VT =1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.

Fin

10.1109/iedm.2013.6724625

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Citations (28)

Channel doping impact on FinFETs for 22nm and beyond

C.-H. Lin R. Kambhampati Robert J. Miller Terence B. Hook A. Bryant

The natural choice to achieve multiple threshold voltages (V th ) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple V th . This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple V th solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as T inv , mobility, electrostatic control and V th mismatch. We also show that V th extraction by the "constant current" method could mislead the DIBL analysis of devices with greatly different channel mobility.

10.1109/vlsit.2012.6242438

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Citations (64)

Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies

R. Bao Kôji Watanabe J. Zhang Hui Zhou M. Sankarapandian

We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.

Nanosheet

10.1109/vlsitechnology18217.2020.9265010

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Citations (11)