W. Badawy

Egyptian Russian University

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A half-pel motion estimation architecture for MPEG-4 applications

Mohammed S. Sayed W. Badawy

This paper presents a novel half-pel motion estimation architecture for MPEG-4 applications. The proposed architecture consists of two parts; interpolation part and full search block matching part. The first part computes the half-pel values by interpolation of the full pixels. The second part searches for the best match to the reference block using full search block matching algorithm to enhance the video quality. The proposed architecture has been prototyped, simulated and synthesized for 0.18 /spl mu/m CMOS technology using TSMC standard cells. At 50 MHz clock frequency the proposed architecture needs 120 /spl mu/sec to compute the motion vectors. The prototyped architecture consumes 247.04 mW with 1.6 V supply voltage and has core area of 0.703 mm/sup 2/.

Interpolation

Parallel architecture

10.1109/iscas.2003.1206093

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Citations (7)

VLSI architecture prototyping of pipelined IIR digital filter

Mehboob Alam W. Badawy

The paper presents a technique for VLSI prototyping pipelining IIR digital filters and offers a detail solution to single chip implementation. The proposed implementation scheme uses the GCLA (generalized cluster look ahead) technique with overflow avoidance to add further stability to the filter. The design using direct and pipelined architecture is implemented on Xilinx V50CS144 device of the Vertex family and optimal results for time were achieved.

Rapid Prototyping

10.1109/ccece.2002.1013086

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Towards Higher Customer Conversion Rate: An Interactive Chatbot Using the BEET Model

W. Badawy Anan El-Helw Aliaa A. A. Youssif

This paper presents an interactive Chatbot that increases the rate of customer conversion by observing the behavior emotion status. The trigger customer action accordingly using a customer behavior analysis model named "Behavioral Emotion Engagement Trigger" BEET model. BEET extends the operation of the Chatbot beyond conversational AI, sentiment analysis to evaluate the emotional status of the customer then it aligns the response using BEET to engage customer along with their own priorities. The performance of the chatbot is measured according to its ability to understand and classify both people and sentiments then it measures their conversion rate.

Chatbot

Sentiment Analysis

Customer engagement

Customer Relationship Management

10.1109/icce-berlin50680.2020.9352152

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Event Detection by Spatio-Temporal Indexing of Video Clips

International Journal of Computer Theory and Engineering (2013)

Shan Du Choudhury A. Rahman Saika Sharmeen W. Badawy

CLIPS

10.7763/ijcte.2014.v6.831

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Citations (2)

Low-power single-bit full adder cells

Canadian Journal of Electrical and Computer Engineering (2003)

Arash Shoarinejad S.A. Ung W. Badawy

The single-bit full adder is one of the main components in almost all logic structures. The performance of logic structures is highly dependent on the adder cells. This paper discusses the performance of single-bit full adders and presents a performance analysis for those cells in CMOS technology. Fourteen single-bit full adders and three new adders, a total of different adder cells, are analyzed in terms of power and delay using 0.35, 0.25 and 0.18 µm TSMC CMOS technology. In addition, this paper discusses the charging-capability parameter of the adder cells, which represents the fan-out of each cell. The charging-capability parameter is capable of describing the performance of the adder cell in a large, as yet unbuilt structure. Hence, the performance analysis of the single-bit full adder relates the design to power, delay, and charging capability of the logic components.

Serial binary adder

Carry-save adder

10.1109/cjece.2003.1426068

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Citations (13)

System on Chip

Kluwer international series in engineering and computer science (2003)

W. Badawy

Application-specific integrated circuit

Integrated circuit design

10.1007/978-1-4615-0351-4_1

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Citations (1)

Low power VLSI architecture for 2D-mesh video object motion tracking

W. Badawy Magdy Bayoumi

This paper presents a low power VLSI architecture for video object motion tracking. Power has been reduced at both algorithmic and arithmetic levels. The video object is modeled as a 2D hierarchical structured mesh, where the deformation of the mesh represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology. Low power has been achieved in the algorithm level by: (1) modeling the mesh into independent triangular patches that can be processed in parallel, (2) each patch is hierarchical triangulated using structured technique, which can be pipelined using simple unit, and (3) using the three steps motion estimation algorithm to simplify the motion estimation of the mesh nodes. On the arithmetic level, low power has been achieved by using multiplication-free affine transformation because of the followed triangle topology. A VLSI architecture is developed based on the proposed algorithm. The architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The first unit is based on parallel block matching motion estimation to optimize the latency. The second uses parallel threads. Each thread implements a pipelined chain of scalable multiplication-free affine units. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML.

Mesh networking

10.1109/iwv.2000.844532

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Citations (6)

Affine schemes in mesh-based video motion compensation

A. Utgikar W. Badawy Gunasekaran Seetharaman Magdy Bayoumi

We evaluate the performances of different implementations of affine transform in a motion compensation architecture based on a hierarchical adaptive structured mesh. The architecture predicts the next video frame using the reference frame, mesh code and mesh node motion vectors. It achieves significant reduction in describing the mesh topology by coding the splitting in recursive triangulation of the initial coarse geometry. It uses a memory serialization unit and one simple warping unit to map the hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. We compare shift-after-difference (SAD), lookup table (LUT) and naive implementations of the affine unit. Computing the affine transform using the multiplication-free SAD algorithm significantly reduces the complexity of the architecture. We establish from simulation results that our multiplication-free SAD affine computation requires far less power and area than other schemes. We discuss the limitations and advantages of different motion compensation schemes. Performance analysis shows that this scheme is suitable for video applications like MPEG and VRML.

Quarter-pixel motion

10.1109/sips.2003.1235662

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Citations (7)

A fast moving object edge detection approach

Yankun Wei Shan Du W. Badawy

This paper proposes a new application for the use of the hierarchical adaptive structure mesh (HASM) along with an edge detection technique. The proposed approach combines still image segmentation and motion segmentation techniques to provide fast processing and higher accuracy of object detection and tracking. The combination of these two techniques reduces the computational cost compared to traditional edge detection approaches and efficiently extracts the moving object edges.

Object-class detection

Tracking (education)

Motion Detection

Segmentation-based object categorization

10.1109/ccece.2002.1013055

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A Novel CMOS Lab-on-a-Chip for Biomedical Applications

1993 IEEE International Symposium on Circuits and Systems (2005)

Yehya H. Ghallab W. Badawy

A novel CMOS integrated laboratory-on-a-chip is presented. It contains both the sensing and actuation parts in a single chip. Experimental and simulation results showed that the chip can inline process the sensing and the actuation and they can trap, concentrate, and quantify biocells. Moreover, the proposed laboratory-on-a-chip can deal with the biological systems at the cell level and it can extract real time information about the biological cells' behaviors using direct measurements.

Lab-on-a-Chip

10.1109/iscas.2005.1464845

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Citations (18)