Old Web
English
Sign In
Acemap
>
authorDetail
>
S. Parke
S. Parke
IBM
Electrical engineering
Electronic engineering
CMOS
Megabit
Engineering
3
Papers
38
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (3)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond
1995
VLSIT | Symposium on VLSI Technology
Gary B. Bronner
H. Aochi
M. Gall
Jeffrey P. Gambino
S. Gernhardt
Erwin Hammerl
Herbert L. Ho
J. Iba
H. Ishiuchi
Mark Anthony Jaso
R. Kleinhenz
T. Mii
M. Narita
Larry Alan Nesbit
W. Neumueller
A. Nitayama
T. Ohiwa
S. Parke
James Gardner Ryan
T. Sato
H. Takato
S. Yoshikawa
Show All
Source
Cite
Save
Citations (22)
A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)
1993
IEDM | International Electron Devices Meeting
Larry Alan Nesbit
Johann Alsmeier
Bomy A. Chen
John K. DeBrosse
P. Faheyk
M. Gall
Jeffrey P. Gambino
S. Gernhard
H. Ishiuchi
R. Kleinhenz
Jack A. Mandelman
T. Mii
Mutsuo Morikado
A. Nitayama
S. Parke
Hing Wong
Gary B. Bronner
Show All
Source
Cite
Save
Citations (15)
Nearly-fully-depleted (NFD), 0.15 mu m SOI CMOS in a CBiCMOS technology
1993
VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
S. Parke
Fariborz Assaderaghi
Chenming Hu
P.K. Ko
Show All
Source
Cite
Save
Citations (1)
1