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Rommel Sánchez Verdejo

Polytechnic University of Catalonia

8

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17

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Rethinking cycle accurate DRAM simulation

2019
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Main memory latency simulation: the missing link

2018
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Enabling a reliable STT-MRAM main memory simulation

2018
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Detailed tuning and validation of hardware simulators through microbenchmarks

2018
- Rommel Sánchez Verdejo
- Petar Radojković
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Enabling a reliable STT-MRAM main memory simulation

2017
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Citations (6)