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A. Nitayama
A. Nitayama
IBM
Megabit
Electronic engineering
Engineering
Trench
Dram
2
Papers
37
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A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond
1995
VLSIT | Symposium on VLSI Technology
Gary B. Bronner
H. Aochi
M. Gall
Jeffrey P. Gambino
S. Gernhardt
Erwin Hammerl
Herbert L. Ho
J. Iba
H. Ishiuchi
Mark Anthony Jaso
R. Kleinhenz
T. Mii
M. Narita
Larry Alan Nesbit
W. Neumueller
A. Nitayama
T. Ohiwa
S. Parke
James Gardner Ryan
T. Sato
H. Takato
S. Yoshikawa
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A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)
1993
IEDM | International Electron Devices Meeting
Larry Alan Nesbit
Johann Alsmeier
Bomy A. Chen
John K. DeBrosse
P. Faheyk
M. Gall
Jeffrey P. Gambino
S. Gernhard
H. Ishiuchi
R. Kleinhenz
Jack A. Mandelman
T. Mii
Mutsuo Morikado
A. Nitayama
S. Parke
Hing Wong
Gary B. Bronner
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Citations (15)
1